1. Field of the Invention
The present invention concerns the digital transmission of data and in particular data transmitted by what is known as SDH (Synchronous Digital Hierarchy).
2. Description of Related Art
Soon after the introduction of 24 and 30 channel PCM systems in the 1960's and early 1970's, time division multiplexing was used to combine the serial bit streams of four such systems into one bit stream for more economical transmission. This became known as second-order digital multiplexing. Subsequent developments have led to third, fourth and fifth-order multiplexers, as progressively more streams are combined. These have traditionally been used in a hierarchy to assemble telephony, data or other traffic to the highest bit rate possible for economic transmission.
At each level in the hierachy several bit streams, known as `tributaries`, are combined or separated by a multiplexer/demultiplexer called a `muldex` (often abbreviated to `mux`). The steps in the hierarchy were chosen to allow flexibility in traffic planning and an economic balance between muldex costs and transmission costs.
Since the mid-1980's there have been moves to define a new muldex hierarchy with larger steps and based on networks which are essentially synchronous. The bandwith properties of optical fibres have changed the balance between transmission and muldex costs, compared to the use of copper cables and radio, and lower overall costs can now be achieved by having larger step sizes. In addition, it is hoped that synchronous operation will provide simpler multiplexing to very high bit rates and lead to lower switching costs together with new switched services.
However SDH will necessarily have to operate in an environment which is not strictly synchronous. The concept of a true synchronous network relies on all connected parties using the same clock. In practice each regional operating authority will require to have control over the security of its own clock and so several `master` clocks will exist, each of high stability, but with some slight drift possible between them. Not all inputs to multiplexers therefore will be truly synchronous. Thus data streams, normally consisting of multiplexed data streams, will, when reaching a network node or switch require justification to match the rate of the incoming data stream which has its own line frequency to that of the receiving node.
Another problem is that in a nominally synchronous network, the input to a multiplexer may suffer from wander because of slow changes in transmission path propagation delay; these changes can be caused by cable temperature shifts and by daily movement of geosynchronous satellites, for example.
Thus multiplexers will have to accept tributary inputs which are plesiochronous. Not only must the multiplexer perform bit interleaving on these inputs but it must also permit the reconstruction of the original tributary signals at the demultiplexers. Accordingly before the tributaries are interleaved they must be brought into true synchronism. This is achieved by "justification". Justification is used in this specification to mean the process of bringing the source frequency of a tributary into synchronism with the traffic or carrier frequency and involves first writing the input data for each tributary into a separate first-in-first-out buffer store (FIFO) using a clock derived from the tributary input and known as the source clock. Next data is read out from all the stores in parallel by a common read-out clock known as the carrier clock. In order to avoid store overflow the read-out or carrier clock is arranged to be faster than the fastest expected input clock. In order to avoid having the store emptied a pulse is occasionally removed from the read clock for each individual tributary so that no data bit is read out of the store. Instead a dummy bit is transmitted which will be removed by the multiplexer at the receive end of the transmission path. This is known as positive justification.
Negative justification is the converse of positive justification and is used when the read clock to the elastic stores is not fast enough always to prevent store overflow. Instead an extra data bit is occasionally removed from the store and transmitted in a spare time slot. Both positive and negative justification may be used in the same multiplexer and this combined process is called positive/zero/negative justification. Justification need not be limited to the insertion or removal of single bits. Instead it can be carried out in multi-bit steps. SDH is based on bytes (8 bits) and justification is accordingly carried out in 8 bit steps.
Positive/zero/negative justification is the justification technique which has been proposed for SDH. In SDH, when the network is synchronous or appears to be synchronous for a period, then no justification may appear for some considerable period. Figures of more than one second are possible as are figures of more than a whole day. The justification process is controlled by what is called a data pointer and the utilisation of the data pointer for this purpose is called pointer processing. When justification does occur 8 more bits or 8 less bits will be sent in a given period. The effect of this is that when a final 2084 kbit/s tributary output is generated which has had either positive or negative justification a phase jump of nearly 4 microseconds will occur. However the specification set by CCITT recommendation G.823 on jitter and wander, in section 3 Table 1, sets a low frequency limit on phases shift of 1.5 bit (732 ns) which will be exceeded. Accordingly users of the SDH network will treat the phase shift introduced by the justification as wander. Such a phase shift can be smoothed out under the CCITT recommendation but the minimum time would be in the order of 50 seconds, with sinusoidal transition. However it is insufficient to allow for the maximum number of 8 bit phase steps on an end to end traffic link to calculate wander requirements. The wander on the links from the network clock reference also have to be added on. If these links are also carried by SDH then 3 times the number of phase steps could be seen. This is because if the nodes at each end are moving their clocks about, because of the phase steps on the clock reference links, then even more phase steps may be forced onto the traffic link. This can cause more than 18 microseconds of wander which will mean that slips will start in the transmitted data causing data loss and degraded transmission.
A method for meeting this problem has been proposed which comprises forcing regular justification of a first polarity onto a carrier frequency, and then generating justification of the opposite polarity at the same rate as the said regular justification if there is no relative drift between the source and the carrier frequencies, and either to increasing or reducing the rate of generation of said justification of opposite polarity in response to drift between the source and carrier frequencies.
However another approach to the problem of rejustification may be preferable. This approach concentrates on the nature of the algorithm which is followed during the rejustification procedures.
3. Summary of the Invention
Accordingly the invention comprises a method of pointer processing a digital TDM data stream at a node of a synchronous SDH transmission network so as to justify the data stream on transmission, the data stream having a specified line frequency and being composed of frames, each frame containing a reference word, and the node of the transmission network having a node frequency, the method comprising storing the incoming data stream in a buffer store at the node, using the line phase reference of the incoming data stream to extract a data pointer from the data stream for each frame, which data pointer indicates the location of the reference word of that frame in the buffer store, and characterised in that a timing pointer is extracted from the incoming data stream utilising the line phase reference and a line clock the frequency of which is a multiple of the line phase reference; the timing pointer so extracted is converted into a phase reference value by utilising the node reference and a node clock; the reference value is utilised to generate a node timing pointer; the node timing pointer is compared with a read address and data pointer; and read-out from the buffer store is justified in accordance with the results of the comparison.
The invention also comprises apparatus for carrying out the aforesaid method.
Consequently changes in the data pointer value can occur without a change in the timing pointer value as well as changes in the timing pointer value occurring without changes in the data pointer value.